A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 349-352

  Lin, Jerry ^a   Duvvury, Charvaka ^a   Haroun, Baher ^a   Oguzman, Ismail ^a   Somayaji, Ananth ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; ELECTROSTATICS; SEMICONDUCTOR DIODES; SEMICONDUCTOR JUNCTIONS; SPURIOUS SIGNAL NOISE;

ELECTROSTATIC DISCHARGES (ESD);

CMOS INTEGRATED CIRCUITS;

EID: 0036923745     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortini, Investigation of Different ESD Protection Strategies Devoted to 3.3 V RF Applications (2 GHZ) in a 0.18 um CMPS Process, Proc. EOS/ESD Symp., pp. 251-259, 2001.
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6. A. Amerasekera, S. Ramaswamy, M-C Chang, and C. Duvvury, Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations, Proc. IRPS, pp.318-326, 1996.
7. K-H. Oh, C. Duvvury, C. Sailing, K. Banerjee, and R. W. Dutton, Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design, Proc. IRPS, pp. 226-234, 2001.
8. A. Amerasekera and C. Duvvury, The impact of technology scaling on ESD robustness and protection circuits in CMOS technology, Proc. EOS/ESD Symp., pp. 237-245, 1994.