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Volumn 4547 LNCS, Issue , 2007, Pages 40-54

VLSI implementation of a functional unit to accelerate ECC and AES on 32-bit processors

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; EMBEDDED SYSTEMS; PROGRAM PROCESSORS; PUBLIC KEY CRYPTOGRAPHY;

EID: 38149011501     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-73074-3_5     Document Type: Conference Paper
Times cited : (8)

References (20)
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    • Bertoni, G., Breveglieri, L., Fragneto, P., Macchetti, M., Marchesin, S.: Efficient software implementation of AES on 32-bit platforms. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 159-171. Springer Verlag, Heidelberg (2003)
  • 4
    • 38149048685 scopus 로고    scopus 로고
    • Gaisler, J.: The LEON-2 Processor User's Manual (Version 1.0.10) (2003) Available for download at http://www.gaisler.com/doc/leon2-1.0.10.pdf
    • Gaisler, J.: The LEON-2 Processor User's Manual (Version 1.0.10) (2003) Available for download at http://www.gaisler.com/doc/leon2-1.0.10.pdf
  • 6
    • 35048898295 scopus 로고    scopus 로고
    • m). In: Chae, K.-J., Yung, M. (eds.) Information Security Applications -WISA 2003. LNCS, 2908, pp. 227-243. Springer Verlag, Heidelberg (2003)
    • m). In: Chae, K.-J., Yung, M. (eds.) Information Security Applications -WISA 2003. LNCS, vol. 2908, pp. 227-243. Springer Verlag, Heidelberg (2003)
  • 7
    • 38149113740 scopus 로고    scopus 로고
    • Cryptography instruction set extensions to the SPARC V8 architecture. Preprint
    • submitted for publication
    • Großschädl, J., Tillich, S., Szekely, A., Wurm, M.: Cryptography instruction set extensions to the SPARC V8 architecture. Preprint, submitted for publication
    • Großschädl, J.1    Tillich, S.2    Szekely, A.3    Wurm, M.4
  • 11
    • 84886492262 scopus 로고    scopus 로고
    • m) ALU: An implementation for a cryptographic processor. In: Proceedings of the 17th IEEE Workshop on Signal Processing Systems (SIPS 2003), pp. 63-68. IEEE, New York (2003)
    • m) ALU: An implementation for a cryptographic processor. In: Proceedings of the 17th IEEE Workshop on Signal Processing Systems (SIPS 2003), pp. 63-68. IEEE, New York (2003)
  • 13
    • 34547695808 scopus 로고    scopus 로고
    • National Institute of Standards and Technology, Standard November, Available online at
    • National Institute of Standards and Technology. FIPS-197: Advanced Encryption Standard (November 2001) Available online at http://www.itl.nist.gov/ fipspubs/
    • (2001) FIPS-197: Advanced Encryption
  • 14
    • 1942457187 scopus 로고    scopus 로고
    • Theoretical Use of Cache Memory as a Cryptanalytic Side-Channel
    • Technical Report CSTR-02-003, Department of Computer Science, University of Bristol June
    • Page, D.: Theoretical Use of Cache Memory as a Cryptanalytic Side-Channel. Technical Report CSTR-02-003, Department of Computer Science, University of Bristol (June 2002)
    • (2002)
    • Page, D.1
  • 15
    • 85099426992 scopus 로고    scopus 로고
    • m). In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, 1965, pp. 277-292. Springer Verlag, Heidelberg (2000)
    • m). In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 277-292. Springer Verlag, Heidelberg (2000)
  • 17
    • 24944503645 scopus 로고    scopus 로고
    • Accelerating AES using instruction set extensions for elliptic curve cryptography
    • Gervasi, O, Gavrilova, M, Kumar, V, Laganà, A, Lee, H.P, Mun, Y, Taniar, D, Tan, C.J.K, eds, Computational Science and Its Applications -ICCSA 2005, Springer, Heidelberg
    • Tillich, S., Großschädl, J.: Accelerating AES using instruction set extensions for elliptic curve cryptography. In: Gervasi, O., Gavrilova, M., Kumar, V., Laganà, A., Lee, H.P., Mun, Y., Taniar, D., Tan, C.J.K. (eds.) Computational Science and Its Applications -ICCSA 2005. LNCS, vol. 3481, pp. 665-675. Springer, Heidelberg (2005)
    • (2005) LNCS , vol.3481 , pp. 665-675
    • Tillich, S.1    Großschädl, J.2
  • 18
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    • Tillich, S., Großschädl, J.: Instruction set extensions for efficient AES implementation on 32-bit processors. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, 4249, pp. 270-284. Springer, Heidelberg (2006)
    • Tillich, S., Großschädl, J.: Instruction set extensions for efficient AES implementation on 32-bit processors. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 270-284. Springer, Heidelberg (2006)
  • 19
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    • Tillich, S., Großschädl, J., Szekely, A.: An instruction set extension for fast and memory-efficient AES implementation. In: Dittmann, J., Katzenbeisser, S., Uhl, A. (eds.) CMS 2005. LNCS, 3677, pp. 11-21. Springer, Heidelberg (2005)
    • Tillich, S., Großschädl, J., Szekely, A.: An instruction set extension for fast and memory-efficient AES implementation. In: Dittmann, J., Katzenbeisser, S., Uhl, A. (eds.) CMS 2005. LNCS, vol. 3677, pp. 11-21. Springer, Heidelberg (2005)
  • 20
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    • Trusted Computing Group. TCG Specification Architecture Overview (Revision 1.2) (April 2004), Available for download at https://www. trustedcomputinggroup.org/groups/TCG-1_0_Architecture-Overview.pdf
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.