Low-Power design of a functional unit for arithmetic in finite fields GF(p) and GF(2m)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2908, Issue , 2004, Pages 227-243

  Großschädl, Johann ^a   Kamendje, Guy Armand ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Elliptic curve cryptography; Finite fields; Instruction set extensions; Multi application smart cards; Unified multiplier datapath

Indexed keywords

CRYPTOGRAPHY; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; GEOMETRY; PUBLIC KEY CRYPTOGRAPHY; SECURITY OF DATA; SMART CARDS; TRANSPORTATION;

DATA PATHS; ELLIPTIC CURVE CRYPTOGRAPHY; FINITE FIELDS; INSTRUCTION SET EXTENSION; MULTIAPPLICATION SMART CARDS;

FINITE ELEMENT METHOD;

EID: 35048898295     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-24591-9_18     Document Type: Article

References (26)

1. ARM Limited. ARM SecurCore Solutions. Product brief, available for download at http://www.arm.com/aboutarm/4XAFLB/File/SecurCores.pdf, 2002.
2. n) Galois field multipliers. In Conference Record of the 36th Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 1619-1623. IEEE, 2002.
3. I. F. Blake, G. Seroussi, and N. P. Smart. Elliptic Curves in Cryptography. Cambridge University Press, 1999.
4. M. Bucci. Dual mode (integer, polynomial) fast modular multipliers. Presentation at the Rump Session of EUROCRYPT '97, Konstanz, Germany, May 13, 1997.
5. 2[x]. In Cryptographic Hardware and Embedded Systems - CHES 2003, LNCS 2779, pp. 203-213. Springer Verlag, 2003.
6. m) on digital signal processors. In Proceedings of the 22nd IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP '97), vol. 1, pp. 631-634. IEEE, 1997.
7. A. A. Farooqui and V. G. Oklobdžija. General data-path organization of a MAC unit for VLSI implementation of DSP processors. In Proceedings of the 31st IEEE Int. Symposium on Circuits and Systems (ISCAS '98), vol. 2, pp. 260-263. IEEE, 1998.
8. J. R. Goodman and A. P. Chandrakasan. An energy efficient reconfigurable publickey cryptography processor architecture. In Cryptographic Hardware and Embedded Systems - CHES 2000, LNCS 1965, pp. 175-190. Springer Verlag, 2000.
9. J. Großschädl. A unified radix-4 partial product generator for integers and binary polynomials. In Proceedings of the 35th IEEE Int. Symposium on Circuits and Systems (ISCAS 2002), vol. 3, pp. 567-570. IEEE, 2002.
10. m). In Proceedings of the 14th IEEE Int. Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), pp. 455-468. IEEE Computer Society Press, 2003.
11. J. Großschädl and G.-A. Kamendje. A single-cycle (32 × 32 + 32 + 64)-bit multiply/accumulate unit for digital signal processing and public-key cryptography. Accepted for presentation at the 10th IEEE Int. Conference on Electronics, Circuits and Systems (ICECS 2003), scheduled for Dec. 14-17, 2003 in Sharjah, U.A.E.
12. H. Handschuh and P. Paillier. Smart card crypto-coprocessors for public-key cryptography. In Smart Card Research and Applications - CARDIS '98, LNCS 1820, pp. 372-379. Springer Verlag, 2000.
13. Z. Huang. High-Level Optimization Techniques for Low-Power Multiplier Design. Ph.D. Thesis, University of California, Los Angeles, CA, USA, 2003.
14. k). Designs, Codes and Cryptography, 14(1):57-69, Apr. 1998.
15. O. L. MacSorley. High-speed arithmetic in binary computers. Proceedings of the IRE, 49(1):67-91, Jan. 1961.
16. m). Journal of VLSI Signal Processing, 15(3):233-245, Mar. 1997.
17. MIPS Technologies, Inc. MIPS32 4Km™ processor core family data sheet. Available for download at http://www.mips.com/publications/index.html, 2001.
18. MIPS Technologies, Inc. SmartMIPS Architecture Smart Card Extensions. Product brief, available for download at http://www.mips.com/ProductCatalog/ P_SmartMIPSASE/SmartMIPS.pdf, 2001.
19. E. M. Nahum, S. W. O'Malley, H. K. Orman, and R. C. Schroeppel. Towards high performance cryptographic software. In Proceedings of the 3rd IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems (HPCS '95), pp. 69-72. IEEE, 1995.
20. V. G. Oklobdžija. Design and analysis of fast carry-propagate adder under nonequal input signal arrival profile. In Conference Record of the 28th Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 1398-1401. IEEE, 1994.
21. V. G. Oklobdžija, D. Villeger, and S. S. Liu. A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Transactions on Computers, 45(3):294-306, Mar. 1996.
22. B. Parhami. Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press, 2000.
23. J. M. Rabaey. Digital Integrated Circuits - A Design Perspective. Prentice Hall, 1996.
24. O. Salomon, J.-M. Green, and H. Klar. General algorithms for a simplified addition of 2's complement numbers. IEEE Journal of Solid-State Circuits, 30(7):839-844, July 1995.
25. A. Satoh and K. Takano. A scalable dual-field elliptic curve cryptographic processor. IEEE Transactions on Computers, 52(4):449-460, Apr. 2003.
26. m). In Cryptographic Hardware and Embedded Systems - CHES 2000, LNCS 1965, pp. 277-292. Springer Verlag, 2000.