RoMultiC: Fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices

Proceedings - 2005 IEEE International Conference on Field Programmable Technology

Volumn 2005, Issue , 2005, Pages 129-136

  Tunbunheng, Vasutan ^a   Suzuki, Masayasu ^a   Amano, Hideharu ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COARSE GRAIN RECONFIGURABLE SYSTEMS; DATA MULTICASTING; DUPLICATED CONFIGURATION DATA; ROW MULTICAST CONFIGURATION (ROMULTIC); BIT MAPS; CLOCK CYCLES; COARSE-GRAIN RECONFIGURABLE; ELEMENT ARRAY; EVALUATION RESULTS; HIGH SPEED; PROCESSING ELEMENTS; RECONFIGURABLE DEVICES; RECONFIGURABLE-SYSTEMS; SIMPLE++;

DATA PROCESSING; DIGITAL STORAGE; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; STORAGE ALLOCATION (COMPUTER); COMPUTER AIDED DESIGN; RECONFIGURABLE ARCHITECTURES; STRUCTURAL DESIGN;

MULTICASTING;

EID: 33846633323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2005.1568536     Document Type: Conference Paper

References (9)

1. T.Sugawara, K.Ide and T.Sato, "Dynamically Reconfigurable Processor Implemented with IPFlex's DAPDNA Tecnhonology," IEICE Trans. On Inf. & Syst. Vol.E87-D, No. 8, pp. 1997-2003, May, (2004).
2. M.Motomura, "A Dynamically Reconfigurable Processor Architecture," Microprocessor Forum, Oct. (2002).
3. V. Baumgarte, G. Ehlers, F. May, A. Nuckel, M. Vorbach, and M. Weinhardt, "PACT XPP - A Self-Reconfigurable Data Processing Architecture", The Journal of Supercomputing, 26(2): 167-184, Sept. (2003).
4. T.Kurose, and et.al., "A 90nm embedded DRAM single chip LSI with a 3D graphics, H.264 codec engine and a reconfigurable processor," Hot Chips 16, (2004).
5. T. Kitaoka, H.Amano and K.Anjo, "Reducing the configuration loading time of a coarse grain multicontext reconfigurable device," in Proc. FPL (LNCS2778), pp.171-180, (2003).
6. H.Singh, M-H.Lee, G.Lu, F.J.Kurdahi, N.Bagherzadeh, and E.M.Chaves, "MorphoSys: An Intergrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications", IEEE Trans. on Computers, Vol.49, no.5, pp.465-480, (2000).
7. Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, and Masayasu Suzuki, "Techniques for Virtual Hardware on a Dynamic Reconfigurable Processor -An approach to tough cases", Proceedings of International Conference on Field Programmable Logic and Application (FPL2004), pp.464-473, Sept. (2004).
8. Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa and Hideharu Amano, "Stream Applications on the Dynamically Reconfigurable Processor", Proc.of IEEE International Conference on Field-Programmable Technology (FPT'04), pp.137-152, Dec. (2004).
9. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, "Using the KressArray for Configurable Computing", Proceedings of SPIE Vol. 3526, Conference on Configurable Computing: Technology and Applications, Boston, USA, Nov. 2-3, (1998).