Hardware cost analysis for weakly programmable processor arrays

2006 International Symposium on System-on-Chip, SOC

Volumn , Issue , 2006, Pages

  Kissler, Dmitrij ^a   Hannig, Frank ^a   Kupriyanov, Alexey ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHLORINE COMPOUNDS; COST ACCOUNTING; INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; TECHNOLOGY; TELECOMMUNICATION;

APPLICATION FIELDS; COARSE-GRAINED RECONFIGURABLE ARCHITECTURES; DEGREE OF PARALLELISM; EMBEDDED DEVICES; HARDWARE COSTS; INTERNATIONAL SYMPOSIUM; MULTIPLE LEVELS; NEW CLASS; PAPER TECHNOLOGY; PARALLEL HARDWARE; PROCESSOR ARRAYS; SPEED REQUIREMENTS; SYSTEM ON CHIPS; WIRELESS COMMUNICATION;

COST BENEFIT ANALYSIS;

EID: 50049112867     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2006.321996     Document Type: Conference Paper

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