Defects tolerant logic gates for unreliable future nanotechnologies

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4507 LNCS, Issue , 2007, Pages 422-429

  Anghel, L ^a   Nicolaidis, M ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FAULT TOLERANCE; NANOTECHNOLOGY;

DEFECT DENSITIES; MEMORY CELLS; MULTIPLE FAULT TOLERANT;

LOGIC GATES;

EID: 38049101025     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-73007-1_52     Document Type: Conference Paper

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