PMOS hole mobility enhancement through SiGe conductive channel and highly compressive ILD-SiNx stressing layer

IEEE Electron Device Letters

Volumn 29, Issue 1, 2008, Pages 86-88

  Liao, Wen Shiang ^a   Liaw, Yue Gie ^b   Tang, Mao Chyuan ^a   Chen, Kun Ming ^c   Huang, Sheng Yi ^a   Peng, C Y ^d   Liu, Chee Wee ^d  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b Silicon Integrated Systems group   (Taiwan)

^c NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

^d NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Contact etching stop layer (CESL); Mobility; PMOS; SiGe channel; Stressing layer

Indexed keywords

ELECTRIC CURRENTS; ETCHING; GATES (TRANSISTOR); HOLE MOBILITY; SEMICONDUCTING SILICON COMPOUNDS;

CONDUCTIVE CHANNEL; CONTACT-ETCHING STOP LAYER (CESL); POSITIVE CHANNEL METAL OXIDE SEMICONDUCTOR (PMOS); STRESSING LAYER;

MOSFET DEVICES;

EID: 37549052463     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.910794     Document Type: Article

References (14)

1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
2. T. Skotnicki, J. A. Hutchby, T. J. King, H.-S. P. Wong, and F. Boeuf, "The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance," IEEE Circuits Devices Mag., vol. 21, no. 1, pp. 16-26, Jan./Feb. 2005.
3. Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T. J. King, J. Bokor, and C. Hu, "Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 279-286, Feb. 2002.
4. Y. C. Yeo, Q. Lu, T. J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro, and J. Sakai, "Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium," in IEDM Tech. Dig., Dec. 2000, pp. 753-756.
5. 0.83 channel metal-oxide-semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition," Appl. Phys. Lett., vol. 76, no. 26, pp. 3920-3922, Jun. 2000.
6. C. Jungermann, S. Keith, and B. Meinerzhagen, "Full-band Monte Carlo simulation of a 0.12 μm-Si-PMOSFET with and without a strained SiGe-channel," in IEDM Tech. Dig., Dec. 1998, pp. 897-900.
7. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K. C. Saraswat, "High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low hand-to-hand tunneling leakage: Experiments," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 990-999, May 2006.
8. L. Washington et al., "pMOSFET with 200% mobility enhancement induced by multiple stressors," IEEE Electron Device Lett., vol. 27, no. 6, pp. 511-513, Jun. 2006.
9. S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, "A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films," in IEDM Tech. Dig., Dec. 2004, pp. 213-216.
10. C. T. Lin, Y. K. Fang, W. K. Yeh, C. M. Lai, C. H. Hsu, L. W. Cheng, and G. H. Ma, "Impacts of notched-gate structure on contact etch stop layer (CESL) stressed 90-nm nMOSFET," IEEE Electron Device Lett., vol. 28, no. 5, pp. 376-378, May 2007.
11. R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, "Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance," in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
12. A. V.-Y. Thean, L. Prabhu, V. Vartanian, M. Ramon, B.-Y. Nguyen, T. White, H. Collard, Q.-H. Xie, S. Murphy, J. Cheek, S. Venkatesan, J. Mogab, C. H. Chang, Y. H. Chiu, H. C. Tuan, Y. C. See, M. S. Liang, and Y. C. Sun, "Uniaxial-biaxial stress hybridization for super-critical strained-Si directly on insulator (SC-SSOI) PMOS with different channel orientations," in IEDM Tech. Dig., Dec. 2005, pp. 509-512.
13. S. Jakschik, T. Hoffman, H.-J. Cho, A. Veloso, R. Loo, S. Hyun, H. Sorada, A. Inoue, M. D. Potter, G. Eneman, S. Severi, P. Absil, and S. Biesemans, "A 50 nm high-k poly silicon gate stack with a buried SiGe channel," in Proc. VLSI-TSA, 2007, p. 30.
14. 1-x PMOS," IEEE Electron Device Lett., vol. 12, no. 4, pp. 154-156, Apr. 1991.