The vector fixed point unit of the synergistic processor element of the cell architecture processor

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 203-206

  Mading N ^a   Leenstra, J ^a   Pille, J ^a   Sautter, R ^a   Buttner S ^a   Ehrenreich, S ^a   Haller, W ^a  

^a IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

FABRICATION; INTEGER PROGRAMMING; MULTIMEDIA SYSTEMS; NETWORKS (CIRCUITS); ROTATING MACHINERY; VECTORS;

FIXED POINT UNIT (FXU); INTEGER ARITHMETICS;

SIGNAL PROCESSING;

EID: 33749187458     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541595     Document Type: Conference Paper

References (3)

1. B. Flachs et al., "The Microarchitecture of the Synergistic Processing Unit of Cell Architecture Processor," ISSCC 2005, pp. 134-135
2. M. M. Ziegler et al., "A Unified Design Space for Regular Parallel Prefix Adders", DATE 2004
3. J. Park et al., "470ps 64bit Parallel binary Adder", Symposium on VLSI Circuits, pp. 192-193, 2000