A customized cross-bar for data-shuffling in domain-specific SIMD processors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4415 LNCS, Issue , 2007, Pages 57-68

  Raghavan, Praveen ^a,b   Munaga, Satyakiran ^a,b   Ramos, Estela Rey ^a,c   Lambrechts, Andy ^a,b   Jayapala, Murali ^a   Catthoor, Francky ^a,b   Verkest, Diederik ^a,b,d  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c UNIVERSITY OF VIGO   (Spain)

^d VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; SOFTWARE DESIGN;

CROSSBAR; CUSTOM SHUFFLERS; DATA SHUFFLING;

EMBEDDED SYSTEMS;

EID: 37249051807     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-71270-1_5     Document Type: Conference Paper

References (22)

1. Ruchira Sasanka. Energy Efficient Support for All levels of Parallelism for Complex Media Applications. PhD thesis, University of Illinois at Urbana-Champaign, June 2005.
2. Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott Mahlke, Trevor Mudge, and Krisztian Flautner. Software defined radio - a high performance embedded challenge. In Proc. 2005 Intl. Conference on High Performance Embedded Architectures and Compilers (HiPEAC), November 2005.
3. IBM, http://www.research.ibm.com/cell/. The Cell Microprocessor, 2005.
4. K. Van Berkel, F. Heinle, P. Meuwissen, K. Moerman, and M. Weiss. Vector processing as an enabler for software-defined radio in handsets from 3G+WLAN onwards. In Proc. of Software Defined Radio Technical Conference, pages 125-130, November 2004.
5. Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, and K. Flautner. SODA: A low-power architecture for software radio. In Proc of ISCA, 2006.
6. Freescale Semiconductor, http://www.freescale.com/files/32bit/doc/ refjnanual/MPC7400UM.pdf?srch=l. Altivec Velocity Engine.
7. Intel, http://www.intel.com/support/processors/ sb/cs-001650.htm. Streaming SIMD Extension 2 (SSE2).
8. Freescle Semiconductor, http://www.freescale.com/webapp/sps/site/ overview.jsp?nodeId=0162468rH3bTdGmKqW5Nf2. Altivec Engine Benchmarks, 2006.
9. Hugo DeMan. Ambient intelligence: Giga-scale dreams and nano-scale realities. In Proc of ISSCC, Keynote Speech, February 2005.
10. Jose Duato, Sudhakar Yalamanchili, and Lionel Ni. Interconnection Networks: an Engineering Approach. IEEE Computer Society, 1997.
11. Nabanita Das, B.B. Bhattacharya, R. Menon, and S.L. Bezrukov. Permutation admissibility in shuffle-exchange networks with arbitrary number of stages. In Intl Conference on High Performance Computing (HIPC), pages 270-276, 1998.
12. H. Cam and J.A.B. Fortes. Rearrangeability of shuffle-exchange networks. In Proc. of Frontiers of Massively Parallel Computation, pages 303 - 314, 1990.
13. I.D. Scherson, P.F. Corbett, and T. Lang. An analytical characterization of generalized shuffle-exchange networks. In IEEE Proc of Computer and Communication Societies (INFOCOM), pages 409 - 414, 1990.
14. Krishnana Padmanabhan. Design and analysis of even-sized binary shuffle-exchange networks for multiprocessors. In IEEE Transactions on Parallel and Distributed Systems, pages 385-397, 1991.
15. S. Diana Smith and H.J. Siegel. An emulator network for SIMD machine interconnect networks. In Computers, pages 232-241, 1979.
16. Krishnan Padmanabhan. Cube structures for multiprocessors. Commun. ACM, 33(1):43-52, 1990.
17. J.P.McGregor and R.B. Lee. Architecture techniques for acclerating subword permutations with repetitions. In Trans. on VLSI, pages 325-335, 2003.
18. X. Yang, M. Vachharajani, and R.B. Lee. Fast subword permutation instructions based on butterfly networks. In Proc of SPIE, Media Processor, pages 80-86, 2000.
19. J.P. McGregor and R.B. Lee. Architectural enhancements for fast subword permutations with repetitions in cryptographic applications. In Proc of ICCD, 2001.
20. A. Elnaggar, M. Aboelaze, and A. Al-Naamany. A modified shuffle-free architecture for linear convolution. In Trans on Circuits and Systems II, pages 862-866, 2001.
21. Synopsys, Inc. Physical Compiler User Guide, 2006.
22. Mentor Graphics. ModelSim SE User's Manual, 2006.