Permutation admissibility in shuffle-exchange networks with arbitrary number of stages

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 1998, Pages 270-276

  Das, Nabanita ^a   Bhattacharya, B B ^a   Menon, R ^a   Bezrukov, S L ^b  

^a INDIAN STATISTICAL INSTITUTE   (India)

^b UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

POLYNOMIAL APPROXIMATION;

ADMISSIBLE SET; ARBITRARY NUMBER; ARBITRARY PERMUTATIONS; INPUT-OUTPUT; MULTISTAGE INTERCONNECTION NETWORK; POLYNOMIAL-TIME; SHUFFLE EXCHANGE NETWORKS; TRANSMISSION DELAYS;

INTERCONNECTION NETWORKS (CIRCUIT SWITCHING);

EID: 84919734499     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HIPC.1998.737998     Document Type: Conference Paper

References (10)

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