A novel circuit-level SEU hardening technique for high-speed SiGe HBT logic circuits

IEEE Transactions on Nuclear Science

Volumn 54, Issue 6, 2007, Pages 2086-2091

  Mukherjee, Tonmoy S ^a,b   Sutton, Akil K ^a,b   Kornegay, Kevin T ^a,b   Krithivasan, Ramkumar ^a,b   Cressler, John D ^a,b   Niu, Guofu ^a,c   Marshall, Paul W ^a,d  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c AUBURN UNIVERSITY   (United States)

^d NONE

Author keywords

Current mode logic (CML); Low voltage logic (LVL); Partial decoupling; Silicon germanium (SiGe); Single event upset (SEU)

Indexed keywords

CURRENT MODE LOGIC (CML); LOW VOLTAGE LOGIC (LVL); SILICON-GERMANIUM (SIGE); SINGLE EVENT UPSET (SEU);

RADIATION HARDENING; REDUNDANCY; SEMICONDUCTING SILICON COMPOUNDS; VOLTAGE CONTROL;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 37249051333     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.908460     Document Type: Conference Paper

References (9)

1. P. W. Marshall, M. A. Carts, A. Campbell, D. McMonow, S. Buchner, R. Stewart, B. Randall, B. Gilbert, andR. A. Reed, "Single event effects in circuit-hardened SiGe HBT logic at gigabit per second data rates," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2669-2674, Dec. 2000.
2. R. Krithivasan, G. Niu, J. D. Cressler, S. M. Currie, K. E. Fritz, R. A. Reed, P. W. Marshall, P. A. Riggs, B. A. Randall, and B. Gilbert. "An SEU hardening approach for high-speed SiGe HBT digital logic," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 2126-2134, Dec. 2003.
3. R. Krithivasan, P. W. Marshall, M. Nayeem, A. K. Sutton, W. M. Kuo, B. M. Haugerud, L. Najafizadeh, J. D. Cressler, M. A. Carts, C. J. Marshall, D. L. Hansen, K.-C. M. Jobe, A. L. McKay, G. Niu, R. Reed, B. A. Randall, C. A. Burfield, M. D. Lindberg, B. K. Gilbert, and E. S. Daniel, "Application of RHBD techniques to seu hardening of third-generation sige HBT logic circuits," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3400-3407, Dec. 2006.
4. D. Kucharski and K. T. Kornegay, "2.5 V 43-45 Gb/s CDR circuit and 55 Gb/s PRBS generator in SiGe using a low-voltage logic family," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2154-2165, Sep. 2006.
5. "SEU Hardening Approach for High Speed Logic," U.S. Patent 5 600 260.
6. S. E. Kerns and B. D. Shafer, "The design of radiation-hardened ICs for space: A compendium of approaches," Proc. IEEE, vol. 76, no. 11, pp. 1470-1509, Nov. 1988.
7. T in a manufacturable technology," IEEE Elect. Dev. Lett., vol. 23, no. 5, pp. 258-260, May 2002.
8. G. Niu, J. D. Cressler, M. Shoga, K. Jobe, P. Chu, and D. L. Harame, "Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2682-2689, Dec. 2000.
9. R. Krithivasan, Y. Lu, J. D. Cressler, J. S. Rieh, M. H. Khater, D. Ahlgren, and G. Freeman, "Half-terahertz operation of SiGe HBTs," IEEE Electron Device Lett., vol. 27, no. 7, pp. 567-569, Jul. 2006.