An SEU Hardening Approach for High-Speed SiGe HBT Digital Logic

IEEE Transactions on Nuclear Science

Volumn 50, Issue 6 I, 2003, Pages 2126-2134

  Krithivasan, Ramkumar ^a   Niu, Guofu ^b   Cressler, John D ^a   Currie, Steve M ^c   Fritz, Karl E ^c   Reed, Robert A ^d   Marshall, Paul W ^d   Riggs, Pamela A ^c   Randall, Barbara A ^c   Gilbert, Barry ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AUBURN UNIVERSITY   (United States)

^c MAYO CLINIC   (United States)

^d NASA GODDARD SPACE FLIGHT CENTER   (United States)

Author keywords

Charge collection; Circuit modeling; Current steering logic; HBT; SiGe; Single event effects (SEE)

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; HARDENING; INTEGRATED CIRCUIT LAYOUT; IONIZING RADIATION; MATHEMATICAL MODELS; SPACE APPLICATIONS;

CHARGE COLLECTION; CIRCUIT MODELING; CURRENT-STEERING LOGIC; SIGE; SINGLE-EVENT EFFECTS (SEE);

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 10744221927     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2003.822094     Document Type: Conference Paper

References (8)

1. "SEU Hardening Approach for High Speed Logic," U.S. patent 5 600 260.
2. P. Marshall, M. A. Carts, A. Campbell, D. McMorrow, S. Buchner, R. Stewart, B. Randall, B. Gilbert, and R. Reed, "Single event effects in circuit hardened SiGe HBT logic at gigabit per second data rate," IEEE Trans. Nucl. Sci., vol. 47, pp. 2669-2674, Dec. 2000.
3. G. Niu, R. Krithivasan, J. D. Cressler, P. A. Riggs, B. A. Randall, P. W. Marshall, R. A. Reed, and B. Gilbert, "A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures," IEEE Trans. Nucl. Sci., vol. 49, pp. 3107-3114, Dec. 2002.
4. D. C. Ahlgren, M. Gilbert, D. Greenberg, J. Jeng, J. Malinowski, D. Nguyen-Ngoc, K. Schonenberg, K. Stein, R. Groves, K. Walter, G. Hueckel, D. Colavito, G. Freeman, D. Sunderland, D. L. Harame, and B. Meyerson, "Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace," in Proc. Tech. Dig. IEEE Int. Electron Devices Meeting, San Francisco, CA, 1996, pp. 859-862.
5. 2-D Semiconductor Device Simulator, 1997. MEDICI 4.0, Synopsis!.
6. G. Niu, J. D. Cressler, M. Shoga, K. Jobe, P. Chu, and D. L. Harame, "Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs," IEEE Trans. Nucl. Sci., vol. 47, pp. 2682-2689, Dec. 2000.
7. M. Varadharajaperumal, G. Niu, R. Krithivasan, J. D. Cressler, R. A. Reed, P. W. Marshall, G. Vizkelethy, P. E. Dodd, and A. J. Joseph, "3-D simulation of heavy-ion induced charge collection in SiGe HBTs," IEEE Trans. Nucl. Sci., vol. 50, pp. 2191-2198, Dec. 2003.
8. G. Niu, R. Krithivasan, J. D. Cressler, P. Marshall, C. Marshall, R. Reed, and D. L. Harame, "Modeling of single event effects in circuit-hardened high-speed SiGe HBT logic," IEEE Trans. Nucl. Sci., vol. 48, pp. 1849-1854, Dec. 2001.