Design considerations for sub-90-nm split-gate flash-memory cells

IEEE Transactions on Electron Devices

Volumn 54, Issue 11, 2007, Pages 3049-3055

  Saha, Samar K ^a,b  

^a SYNOPSYS INC   (United States)

^b DSM Solutions Inc   (United States)

Author keywords

Coupling ratio; Device simulation; Erase; Flash memory; Nor Flash; Programming; Scaling; Split gate

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

COUPLING RATIO; FLASH MEMORY CELLS; SPLIT GATE;

FLASH MEMORY;

EID: 36248959747     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.907265     Document Type: Article

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