Flash memory-cell characterization using two-transistor cell compact macro-model for system-on-chip design

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5755, Issue , 2005, Pages 79-86

  Chen, Changyuan ^a   Saha, Samar ^a  

^a SILICON STORAGE TECHNOLOGY INC   (United States)

Author keywords

Device scaling; Flash memory cell; SoC; SPICE macro model; SSI flash memory cell; Technology CAD

Indexed keywords

DEVICE-SCALING; FLASH MEMORY CELL; SOC; SPICE MACRO-MODEL; SSI-FLASH MEMORY CELL; TECHNOLOGY CAD;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; STORAGE ALLOCATION (COMPUTER); TRANSISTORS;

FLASH MEMORY;

EID: 25144461540     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.601974     Document Type: Conference Paper

References (13)

1. H. Chang, L.R. Cooke, M. Hunt, G. Martin, A. McNelly, L. Todd, and L. Cooke., "Surviving the SoC Revolution - A Guide to Platform-Based Design", Norwell, MA: Kluwer, 1999.
2. L. Baldi and A. Maurelli, "Embedded non-volatile memories in deep-submicron CMOS," in Proc. ESSDERC, pp. 127-134, 1999.
3. M. Borgatti, A. Rocchi, M. Bisio, M. Besana, L. Navoni, and P.L Rolandi, "A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory Solid-State Circuits," IEEE Journal of Solid-State Circuits, vol. 36, pp. 516-521, 2001.
4. J. Tsouhlarakis, G. Vanhorebeek, G. Verhoeven, J. De Blauwe, S. Kim: D. Wellekens, P. Hendrickx, L. Haspeslagh, J. Van Houdt, and H. Maes, "A flash memory technology with quasi-virtual ground array for low-cost embedded applications," Journal of Solid-State Circuits, vol. 36, pp. 969-978, 2001.
5. J. Van Houdt, L. Haspeslagh, D. Wellekens, L. Deferm, G. Groeseneken, and H.E. Maes, "HIMOS - A high efficiency Flash E2PROM cell for embedded memory applications," IEEE Trans. Electron Devices, vol. 40. pp. 2255-2263, 1993.
6. S. Kianian, A. Levi, D. Lee, and Y.-W. Hu, "A novel 3 volts-only, small sector erase, high density flash E PROM," in 1994 Symp. VLSI Technology Dig. Tech. Papers, vol. 6A, pp. 71-72.
7. R. Mih et al., "0.18um modular triple self-aligned embedded split-gate flash memory," Symp. VLSI Tech., p. 120 (2000)
8. Y. Ma, C. S. Pang, J. Pathak, S. C. Tsao, and C. F. Chang, "A novel high density contactless flash memory array using split-gate source-side injection cell for 5 V-only application," in 1994 Symp. VLSI Technology Dig. Tech. Papers, vol. 5A, pp. 49-50.
9. K. Chang, W. Chen, C. Swift, J. M. Higman, W. M. Paulson, and K. Chang, "A new SONOS memory using source-side injection for programming," IEEE Electron Device Lett., vol. 19, pp. 253-255, 1998.
10. A. T. Wu, T.-Y. Chan, P.-K. Ko, and C. Hu, "A novel high-speed, 5-volt programming EPROM structure with source-side injection," in IEDM Tech. Dig., 1986. pp. 584-587.
11. Y. A. El-Mansy and A. R. Boothroyd, "A simple two-dimensional model for IGFET operation in the saturation region," IEEE Trans. Electron Devices, vol. ED-24, pp. 254-262, 1977.
12. M. El-Banna and M. A. El-Nokali, "A simple analytical model for hot-carrier MOSFET's," IEEE Trans. Electron Devices, vol. 36, pp. 979-986, 1989
13. S. Saha and B. Gadepally, "Technology CAD: Technology modeling, device design and simulation," VLSI Design 2004: Tutorial, Mumbai, India, Jan. 5, 2004.