Impact of BOX/substrate interface on low frequency noise in FD-SOI devices

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6600, Issue , 2007, Pages

  Zafari, L ^a   Jomaah, J ^a   Ghibaudo, G ^a  

^a IMEP LAHC   (France)

Author keywords

BOX material; BOX substrate interface charge fluctuation; Fully depleted SOI; Low frequency noise; Substrate doping; Substrate noise

Indexed keywords

DIELECTRIC MATERIALS; DRAIN CURRENT; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; THICKNESS MEASUREMENT;

INTERFACE CHARGE FLUCTUATION; LOW FREQUENCY NOISE; OXIDE INTERFACES; SUBSTRATE DOPING; SUBSTRATE NOISE;

SPURIOUS SIGNAL NOISE;

EID: 36248955443     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.724671     Document Type: Conference Paper

References (15)

1. K.K. Young, IEEE Transactions on Electron Devices, 36, p. 399402 (1989).
2. J.P. Colinge, "Subthreshold slope of thin-film SOI MOSFETs" IEEE Electron Device Letters, 7, p.244_246 (1986).
3. S.P.Edwards, IEEE Transactions on Electron Devices, 35, p.1012-1020 (1988).
4. A. Viviani, J.P.Raskin, D.Flandre, J.P.Colinge, and D.Vanhoenacker, "Extended study of crosstalk in SOI-SIMOX substrate," IEDM Tech. Dig., pp.713_716, (1995).
5. A.L. McWhorter, "Semiconductor surface physics", University of Pennsylvania Press, Philadelphia (1957).
6. G. Ghibaudo, O. Roux, Ch. Nguyen-Due, F. Balestra, and J. Brini, "Improved analysis of low frequency noise in Field-Effect MOS transistors", Phys. stat. sol (a) 124, 571(1991).
7. G.Ghibaudo, J.Jomaah and F.Balestra, "Impact of gate polysilicon interface on carrier trapping low frequency noise in advanced MOSFETs", Fluctuations and noise Letters, in press, (2006).
8. H-K Lim and J.G.Fossum, "Threshold voltage of thin-film Silicon-on -Insulator (SOI) MOSFETs", IEEE Transactions on Electron Devices, 10, pp.1244_1251, (1983).
9. S.Cristoloveanu and S.S.Li, "Electrical characterisation of SOI materials and devices", Kluwer (1995).
10. S. Haendler, J.Jommah, F.Dieudonné, and F.Balestra, "On the 1/f noise in fully depleted SOI transistors," Proc. Int. Conf Noise Physical Systems 1/f Fluctuations, pp.133_136, (2001).
11. S.Sze, "Physics of semiconductor devices", John Wiley, New York (1981).
12. H.-S.P.Wong,D.J.Frank,andP.M.Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation," IEDM Tech. Dig., pp. 407-410, (1998).
13. R. S. Muller and T. I. Kamins, "Device electronics for integrated circuits," 2nd ed. New York: Wiley, p. 401, (1986)
14. T.Matsumoto, S.Maeda, H.Dang T.Uchida, K.Ota, Y.Hirano, H.Sayama, T.Iwamatsu, T.Ipposhi, H.Oda, S.Maegawa, Y.Inoue, and T.Nishimura, "Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications," IEDM Tech. Dig., pp.663-666, (2002).
15. N.Bresson, S.Cristoloveanu, K.Oshima, C.Mazure, F.Letertre, H.Iwai, "Alternative dielectrics for advanced SOI MOSFETs: thermal properties and short channel effects," IEEE International SOI Conference, pp.62-64, (2004).