Component refinement and CSC-solving for STG decomposition

Theoretical Computer Science

Volumn 388, Issue 1-3, 2007, Pages 243-266

  Schaefer, Mark ^a   Vogler, Walter ^a  

^a UNIVERSITY OF AUGSBURG   (Germany)

Author keywords

Asynchronous circuits; Decomposition; Implementation relation; Petri nets; STG

Indexed keywords

ALGORITHMS; HIERARCHICAL SYSTEMS; INPUT OUTPUT PROGRAMS; POWER SUPPLY CIRCUITS; PROBLEM SOLVING; SIGNAL ANALYSIS;

ASYNCHRONOUS CIRCUITS; HIERARCHICAL DECOMPOSITION; IMPLEMENTATION RELATION;

PETRI NETS;

EID: 35748937315     PISSN: 03043975     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.tcs.2007.08.005     Document Type: Article

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