Logic synthesis for asynchronous circuits based on petri net unfoldings and incremental SAT

Proceedings - Fourth International Conference on Application of Concurrency to System Design, ACSD 2004

Volumn , Issue , 2004, Pages 16-25

  Khomenko, Victor ^a   Koutny, Maciej ^a   Yakovlev, Alex ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

Asynchronous circuits; Logic synthesis; Net unfoldings; Partial order techniques; Petri nets; SAT; Self timed circuits; Signal transition graphs; STG

Indexed keywords

ASYNCHRONOUS CIRCUITS; LOGIC SYNTHESIS; NET UNFOLDINGS; PARTIAL ORDER TECHNIQUES; SAT; SELF-TIMED CIRCUITS; SIGNAL TRANSITION GRAPHS; STG;

BOOLEAN ALGEBRA; CONTROL EQUIPMENT; FINITE AUTOMATA; INFORMATION ANALYSIS; LOGIC CIRCUITS; LOGIC GATES; PETRI NETS; SIGNAL PROCESSING;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 10444269487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSD.2004.1309112     Document Type: Conference Paper

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