Scaling up of wave pipelines

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 439-445

  Fukase, M A ^a   Sato, T ^a   Egawa, R ^a   Nakamura, T ^a  

^a HIROSAKI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; DELAY CIRCUITS; MICROPROCESSOR CHIPS; TIMING CIRCUITS; VLSI CIRCUITS;

WAVE PIPELINING;

LOGIC CIRCUITS;

EID: 0035014652     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)