Delay analysis of neuron-MOS and capacitive threshold-logic

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2000, Pages 932-935

  Celinski, Peter ^a   Al Sarawi, Said ^a   Abbott, Derek ^a  

^a NONE

Author keywords

Capacitive Threshold Logic; Floating gate transistor; Neuron MOS

Indexed keywords

ANALYTIC EXPRESSIONS; CAPACITIVE-THRESHOLD LOGIC; CLOSED FORM; CMOS INVERTERS; DELAY ANALYSIS; FLOATING GATE TRANSISTORS; GATE STRUCTURE; LOGIC CIRCUIT DESIGN; NEURON-MOS; THRESHOLD GATES;

DELAY CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; SWITCHING CIRCUITS; THRESHOLD LOGIC;

LOGIC CIRCUITS;

EID: 1542696094     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.913029     Document Type: Conference Paper

References (13)

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