A new latch-based threshold logic family

Proceedings of the International Semiconductor Conference, CAS

Volumn 2, Issue , 2001, Pages 531-534

  Pǎdure, Marius ^a   Coţofanǎ, Sorin ^a   Dan, Claudius ^a   Bodea, Mircea ^a   Vassiliadis, Stamatis ^a  

^a UNIVERSITY POLITEHNICA OF BUCHAREST   (Romania)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; SEMICONDUCTOR SWITCHES; VOLTAGE CONTROL;

DIFFERENTIAL CURRENT-SWITCH THRESHOLD LOGIC; LATCH-BASED THRESHOLD LOGIC;

THRESHOLD LOGIC;

EID: 0035744389     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Low-power CMOS threshold-logic gate
2. Periodic symmetric functions, serial addition and multiplication with neural networks
3. A threshold logic gate based on clocked coupled inverters
4. Bit-sliced median filter design based on majority gate
5. A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates
6. Ganged CMOS: Trading standby power for speed
7. Neural computing of arithmetic functions
8. A functional MOS transistor featuring gate-level weighted sum and threshold operations
9. Differential current switch logic: A low power DCVS logic family