Impact of gate tunnelling leakage on CMOS circuits with full open defects

Electronics Letters

Volumn 43, Issue 21, 2007, Pages 1140-1142

  Rodriguez Montanes, R ^a   Arumi D ^a   Figueras, J ^a   Eichenberger, S ^b   Hora, C ^b   Kruseman, B ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; ELECTRON TUNNELING; GATE DIELECTRICS; INTERCONNECTION NETWORKS; LEAKAGE CURRENTS;

CMOS CIRCUITS; FLOATING NODES; GATE TUNNELLING;

CMOS INTEGRATED CIRCUITS;

EID: 35148899280     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20072117     Document Type: Article

References (6)

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2. Renovell, M., and Cambon, G.: ' Topology dependence of floating gate faults in MOS integrated circuits ', Electron. Lett., 1986, 22, (3), p. 152-153 10.1049/el:19860106 0013-5194
3. Champac, V.H., Rubio, A., and Figueras, J.: ' Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing ', IEEE Trans. Comput.-Aided Des., 1994, 13, p. 359-369 0278-0070
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