High-κ gate dielectrics with ultra-low leakage current for sub-45nm CMOS

Electronics Letters

Volumn 43, Issue 21, 2007, Pages 1130-1132

  Venkateshan, A ^a   Singh, R ^a   Poole, K F ^a   Harriss, J ^a   Senter, H ^b   Teague, R ^b   Narayan, J ^c  

^a AMRL   (United States)

^b CLEMSON UNIVERSITY   (United States)

^c North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT DENSITY; LEAKAGE CURRENTS; ROBUST CONTROL; STATISTICS; THICKNESS MEASUREMENT;

DIELECTRIC FORMATION; OXIDE THICKNESS; PROCESS VARIATION;

GATE DIELECTRICS;

EID: 35148861087     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20072178     Document Type: Article

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