Application analysis with integrated identification of complex instructions for configurable processors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3254, Issue , 2004, Pages 633-642

  Kavvadias, Nikolaos ^a   Nikolaidis, Spiridon ^a  

^a ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

APPLICATION PARAMETERS; CONFIGURABLE PROCESSORS; DESIGN SPACE EXPLORATION; INSTRUCTION EXTENSIONS; INTEGRATED IDENTIFICATION; PROCESSOR PERFORMANCE; PROGRAMMABLE PLATFORMS; WAVELET/SCALAR QUANTIZATIONS;

PROGRAM PROCESSORS;

EID: 35048900671     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30205-6_65     Document Type: Article

References (15)

1. Jacome, M.F., de Veciana, G.: Design challenges for new application-specific processors. IEEE Design and Test of Computers, Vol. 17, No. 2, (2000) 40-50
2. Gonzalez R.: Xtensa: A configurable and extensible processor. IEEE Micro, Vol. 20, No. 2, (2000) 60-70
3. Altera Nios: http://www.altera.com
4. Gaisler research: http://www.gaisler.com
5. Itoh, M., Higaki, S., Sato, J., Shiomi, A., Takeuchi, Y., Kitajima, A., Imai, M.: PEAS-HI: An ASIP design environment. IEEE Int. Conf. on Computer Design, (2000) 430-436
6. A. Hoffmann et al.: A novel methodology for the design of application-specific instruction set processors (ASIPs) using a machine description language. IEEE Trans, on Computer-Aided Design, Vol. 20, No. 11, (2001) 1338-1354
7. Smith M.D., Holloway G.: An introduction to Machine SUIF and its portable libraries for analysis and optimization. Tech. Rpt., Division of Eng. and Applied Sciences, Harvard University, 2.02.07.15 edition, (2002)
8. Gupta T.V.K., Sharma P., Balakrishnan M., Malik S.: Processor evaluation in an embedded systems design environment., 13th Int. Conf. on VLSI Design, (2000) 98-103
9. Ghazal N., Newton R., Rabaey J.: Retargetable estimation scheme for DSP architecture selection. Asia and South Pacific Design Automation Conf., (2000) 485-489
10. Kim S., Somani A.K.: Characterization of an extended multimedia benchmark on a general purpose microprocessor architecture. Tech. Rpt DCNL-CA-2000-002, DCNL (2000)
11. Lee C., Potkonjak M., Mangione-Smith W.H.: MediaBench: A tool for evaluating and synthesizing multimedia and communication systems. Proc. of the IEEE/ACM Symp. on Microarchitecture, (1997) 330-335
12. Leupers R., Wahlen O., Hohenauer M., Kogel T., Marwedel P.: An executable intermediate representation for retargetable compilation and high-level code optimization. Int. Wkshp. on Systems, Architectures, Modeling and Simulation (SAMOS), Samos, Greece (2003)
13. Clark N., Zhong H., Tang VV., Mahlke S.: Automatic Design of Application Specific Instruction Set Extensions through Dataflow Graph Exploration. Int. Journal of Parallel Programming, Vol. 31, No. 6, (2003) 429-449
14. Hopper T., Brislawn C., Bradley J.: WSQ Grayscale Fingerprint Image Compression Specification, Version 2.0, Criminal Justice Information Services, FBI, Washington, DC (1993)
15. Kumar S., Pires L., Ponnuswamy S., Nanavati C., Golusky, Vojta M., Wadi S., Pandalai D., Spaanenburg H.: A benchmark suite for evaluating configurable computing systems Status, reflections, and future directions. ACM Int. Symp. on FPGAs (2000)