Retargetable estimation scheme for DSP architecture selection

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 485-489

  Ghazal, Naji ^a   Newton, Richard ^a   Rabaey, Jan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE MODELING; DIGITAL SIGNAL PROCESSORS (DSP); DSP APPLICATION; DSP ARCHITECTURES; DSP BENCHMARKS; ESTIMATION SCHEMES; HIGH LEVEL DESCRIPTION; TRUE POTENTIALS;

BENCHMARKING; COMPUTER AIDED DESIGN; DIGITAL SIGNAL PROCESSORS; ESTIMATION; OPTIMIZATION; SIGNAL PROCESSING;

ARCHITECTURE;

EID: 0003604235     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368766     Document Type: Conference Paper

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