Compiler optimization-space exploration

International Symposium on Code Generation and Optimization, CGO 2003

Volumn , Issue , 2003, Pages 204-215

  Triantafyllis, S ^a   Vachharajani, M ^a   Vachharajani, N ^a   August, D I ^a  

^a Princeton University   (United States)

Author keywords

Computer architecture; Computer science; Cost function; Degradation; Microarchitecture; Optimizing compilers; Parallel processing; Performance gain; Production; Resource management

Indexed keywords

BENCHMARKING; CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER RESOURCE MANAGEMENT; COMPUTER SCIENCE; COSINE TRANSFORMS; COST FUNCTIONS; DEGRADATION; ITERATIVE METHODS; NETWORK COMPONENTS; OPTIMIZATION; PRODUCTION; SPACE RESEARCH;

MICRO ARCHITECTURES; OPTIMIZING COMPILERS; PARALLEL PROCESSING; PERFORMANCE GAIN; RESOURCE MANAGEMENT;

PROGRAM COMPILERS;

EID: 67650534864     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2003.1191546     Document Type: Conference Paper

References (24)

1. Intel Corporation, IA-64 Application Developer's Architecture Guide, May 1999.
2. Phillips Corporation, "Phillips Trimedia Processor Homepage," 2002. http://www.semiconductors.philips.com/trimedia/.
3. Equator Corporation, "Equator MAPArchitecture," 2002. http://www.equator.com/products/MAPCAProductBrief.html.
4. D. F. Bacon, S. L. Graham, and O. J. Sharp, "Compiler transformations for high-performance computing," ACM Computing Surveys, vol. 26, no. 4, pp. 345-420, 1994.
5. E. Granston and A. Holler, "Automatic recommendation of compiler options," in Proceedings 4th Feedback Directed Optimization Workshop, December 2001.
6. T. Kisuki, P. M. W. Knijnenburg, M. F. P. O'Boyle, F. Bodin, and H. A. G. Wijshoff, "A feasibility study in iterative compilation," in International Symposium on High Performance Computing, pp. 121-132, 1999.
7. F. Bodin, T. Kisuki, P. M. W. Knijnenburg, M. F. P. O'Boyle, and E. Rohou, "Iterative compilation in a non-linear optimisation space," in Proceedings of the Workshop on Profile and Feedback-Directed Compilation, in Conjunction with the International Conference on Parallel Architectures and Compilation Techniques, October 1998.
8. K. D. Cooper, D. Subramanian, and L. Torczon, "Adaptive optimizing compilers for the 21st century," in Proceedings of the 2001 Symposium of the Los Alamos Computer Science Institute, October 2001.
9. D. L. Whitfield and M. L. Soffa, "An approach for exploring code improving transformations," ACM Transactions on Programming Languages and Systems, vol. 19, pp. 1053-1084, November 1997.
10. J. Llosa, M. Valero, E. Ayguade, and A. Gonzalez, "Modulo scheduling with reduced register pressure," IEEE Transactions on Computers, vol. 47, no. 6, pp. 625-638, 1998.
11. R. Govindarajan, E. R. Altman, and G. R. Gao, "Minimizing register requirements under resource-constrained rate-optimal software pipelining," in Proceedings of the 27th Annual International Symposium on Microarchitecture, December 1994.
12. R. Leupers, "Instruction scheduling for clustered VLIW DSPs," in Proceedings of the International Conference on Parallel Architecture and Compilation Techniques, October 2000.
13. J. R. Goodman and W. C. Hsu, "Code scheduling and register allocation in large basic blocks," in Proceedings of the 1988 International Conference on Supercomputing, pp. 442-452, July 1988.
14. D. G. Bradlee, S. J. Eggers, and R. R. Henry, "Integrating register allocation and instruction scheduling for RISCs," in Proceedings of the 1991 International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 122-131, 1991.
15. W. G. Morris, "CCG: A prototype coagulating code generator," in Proceedings of the SIGPLAN '91 Conference on Programming Language Design and Implementation, (Toronto), pp. 45-58, June 1991.
16. S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, R. A. Bringmann, and W. W. Hwu, "Effective compiler support for predicated execution using the hyperblock," in Proceedings of the 25th International Symposium on Microarchitecture, pp. 45-54, December 1992.
17. D. I. August, W. W. Hwu, and S. A. Mahlke, "A framework for balancing control flow and predication," in International Symposium on Microarchitecture, pp. 92-103, 1997.
18. B. Aarts, M. Barreteau, F. Bodin, P. Brinkhaus, Z. Chamski, H.-P. Charles, C. Eisenbeis, J. Gurd, J. Hoogerbrugge, P. Hu, W. Jalby, P. Knijnenburg, M. O'Boyle, E. Rohou, R. Sakellariou, H. Schepers, A. Seznec, E. A. Sthr, M. Verhoeven, and H. Wijshoff, "OCEANS: Optimizing compilers for embedded HPC applications," Lecture Notes in Computer Science, August 1997.
19. F. Bodin, D. Windheiser, W. Jalby, D. Atapattu, M. Lee, and D. Gannon, "Performance evaluation and prediction for parallel algorithms on the BBN GP1000," in Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 401-413, April 1990.
20. M. Wolf, D. Maydan, and D. Chen, "Combining loop transformations considering caches and scheduling," in Proceedings of the 29th Annual International Symposium on Microarchitecture, pp. 274-286, December 1996.
21. D. I. August, D. A. Connors, S. A. Mahlke, J. W. Sias, K. M. Crozier, B. Cheng, P. R. Eaton, Q. B. Olaniran, and W. W. Hwu, "Integrated predication and speculative execution in the IMPACT EPIC architecture," in Proceedings of the 25th International Symposium on Computer Architecture, pp. 227-237, June 1998.
22. Intel Corporation, Electron C Compiler User's Guide for Linux, 2001.
23. Y.-T. S. Li, S. Malik, and A. Wolfe, "Performance Estimation of Embedded Software with Instruction Cache Modeling," Design Automation of Electronic Systems, vol. 4, no. 3, pp. 257-279, 1999.
24. S. Eranian, "pfmon Performance Monitoring Tool." ftp://ftp.hpl.hp.com/pub/linux-ia64.