Tuned LC clock buffers with static phase adjust

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2007, Pages 519-522

  Reddy, Viswabharath ^a   Titus, Ward ^a   Kenney, Jack ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

Buffers; Circuit tuning; Phase matching; Phase shifters; RLC circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; NATURAL FREQUENCIES; PHASE MATCHING; PHASE SHIFTERS; SIGNAL DETECTION; TRANSCEIVERS; TUNING;

CIRCUIT TUNING; MISMATCHED CENTER FREQUENCIES; RLC CIRCUITS;

BUFFER CIRCUITS;

EID: 34748924136     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2007.380937     Document Type: Conference Paper

References (7)

1. J. Hauenschild et al., "A Plastic Packaged 10 GBPS Clock and Data Recovery 1:4 Demultiplexer with External VCO," IEEE J. of Solid-State Circuits, vol. 31, no. 12, pp. 2056-2059, Dec. 1996.
2. A.J. Drake, et al, "Resonant clocking using distributed parasitic Capacitance," in Proc. Of Int. Custom Integrated Circuits Conf., pp. 647-650, 2003.
3. S.C. Chan, et al, "A 4.6 GHz resonant global, clock distribution network," in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, pp. 342-343, 2004.
4. S. Sidiropoulos et al, "An 800 mW 10 Gb Ethernet transceiver in 0.13 μm CMOS" in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, pp. 168-169, 2004.
5. Y.M. Greshishchev et al., A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate," IEEE J. of Solid-State Circuits, vol. 35, no. 12, pp. 1949-1957, Dec. 2000.
6. J. Kenney et al, "A 9.95-11.3Gbps XFP transceiver in 0.13μm CMOS", in IEEE J. of Solid-State Circuits, vol. 41, no. 12, pp. 2901-2910, Dec 2006.
7. J. Kenney et al, "LC Tank Clock Driver with Automatic Tuning", US Patent No. 7,126,403, Oct. 2006.