A 9.95-11.3-Gb/s XFP transceiver in 0.13-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2901-2909

  Kenney, John G ^a,b   Dalton, Declan ^a,c   Evans, Eric ^a,d   Eskiyerli, Murat Hayri ^a,e   Hilton, Barry ^b   Hitchcox, Dave ^a,d   Kwok, Terence ^d   Mulcahy, Daniel ^a,b   McQuilkin, Chris ^b   Reddy, Viswabharath ^a,b   Selvanayagam, Siva ^a,d   Shepherd, Paul ^d   Titus, Ward S ^a,b   DeVito, Lawrence ^a,b  

^a IEEE   (United States)

^b ANALOG DEVICES INC   (United States)

^c ANALOG DEVICES   (Ireland)

^d Analog Devices Inc UK   (United Kingdom)

^e TOBB UNIVERSITY OF ECONOMICS AND TECHNOLOGY   (Turkey)

Author keywords

Clock and data recovery (CDR); Delay locked loop (DLL); Frequency locked loop (FLL); Phase locked loop (PLL); Transceiver

Indexed keywords

BINARY PHASE DETECTOR; CLOCK AND DATA RECOVERY (CDR); DISPERSION JITTER; FREQUENCY LOCKED LOOP (FLL); PHASE DETECTOR;

BANDWIDTH; BIT ERROR RATE; DATA TRANSFER; JITTER; PHASE LOCKED LOOPS; POWER AMPLIFIERS; TRANSCEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 33845681543     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884344     Document Type: Conference Paper

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