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Volumn E87-A, Issue 12, 2004, Pages 3324-3326

A novel digitally-controlled varactor for portable delay cell design

Author keywords

Cell based; DCO; Digitally controlled varactor (DCV); DLL; Portable delay element

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; DIGITAL CONTROL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES;

EID: 11144332005     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (4)

References (7)
  • 1
    • 0037968905 scopus 로고    scopus 로고
    • A delay-line based DCO for multimedia applications using digital standard cells only
    • Session 24, Feb.
    • E. Roth, M. Thiemann, N. Felber, and W. Fichtner, "A delay-line based DCO for multimedia applications using digital standard cells only," ISSCC Digest of Technical Papers, Session 24, pp.432-433, Feb. 2003.
    • (2003) ISSCC Digest of Technical Papers , pp. 432-433
    • Roth, E.1    Thiemann, M.2    Felber, N.3    Fichtner, W.4
  • 2
    • 0037319653 scopus 로고    scopus 로고
    • An all digital phase-locked loop for high-speed clock generation
    • Feb.
    • C.-C. Chung and C.-Y. Lee, "An all digital phase-locked loop for high-speed clock generation," IEEE J. Solid-State Circuits, vol.38, no.2, pp.347-351, Feb. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , Issue.2 , pp. 347-351
    • Chung, C.-C.1    Lee, C.-Y.2
  • 3
    • 0024091885 scopus 로고
    • A variable digital delay line PLL for CPU-coprocessor synchronization
    • Oct.
    • M.G. Johnson and E.L. Hudson, "A variable digital delay line PLL for CPU-coprocessor synchronization," IEEE J. Solid-State Circuits, vol.23, no.10, pp.1218-1223, Oct. 1988.
    • (1988) IEEE J. Solid-state Circuits , vol.23 , Issue.10 , pp. 1218-1223
    • Johnson, M.G.1    Hudson, E.L.2
  • 4
    • 11144297886 scopus 로고    scopus 로고
    • A robust digital delay line architecture in A 0.13 μm CMOS technology node for reduced design and process sensitivities
    • March
    • P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, and B. Haroun, "A robust digital delay line architecture in A 0.13 μm CMOS technology node for reduced design and process sensitivities," Proc. ISQED, pp.148-153, March 2002.
    • (2002) Proc. ISQED , pp. 148-153
    • Raha, P.1    Randall, S.2    Jennings, R.3    Helmick, B.4    Amerasekera, A.5    Haroun, B.6
  • 5
    • 0142008437 scopus 로고    scopus 로고
    • Portable digital clock generator for digital signal processing applications
    • Sept.
    • T. Olsson and P. Nilsson, "Portable digital clock generator for digital signal processing applications," Electron. Lett., vol.39, pp.1372-1374, Sept. 2003.
    • (2003) Electron. Lett. , vol.39 , pp. 1372-1374
    • Olsson, T.1    Nilsson, P.2
  • 6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.