Multiplierless, folded 9/7- 5/3 wavelet VLSI architecture

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 9, 2007, Pages 770-774

  Martina, Maurizio ^a   Masera, Guido ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Filter bank (FB); JPEG2000; multiplierless implementation; VLSI; wavelet

Indexed keywords

COMPUTER ARCHITECTURE; FILTER BANKS; FREQUENCY MULTIPLYING CIRCUITS; IMAGE COMPRESSION; WAVE FILTERS;

MULTIPLIERLESS ARCHITECTURE;

VLSI CIRCUITS;

EID: 34648831843     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.900354     Document Type: Article

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