A 5mA 0.6μm CMOS miller-compensated LDO regulator with -27dB worst-case power-supply rejection using 60pF of on-chip capacitance

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 520-521

  Gupta, Vishal ^a   Rincón Mora, Gabriel A ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHIP SCALE PACKAGES; POWER SUPPLY CIRCUITS; VOLTAGE REGULATORS;

MILLER-COMPENSATED SOC LDO REGULATORS; NMOS DEVICES; WORST-CASE POWER-SUPPLY;

CMOS INTEGRATED CIRCUITS;

EID: 34548853721     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373523     Document Type: Conference Paper

References (8)

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