A supply-noise-insensitive CMOS PLL with a voltage regulator using dc-dc capacitive converter

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 10, 2001, Pages 1453-1463

  Lee, Chang Hyeon ^a,b,c   McClellan, Kelly ^a,d   Choma Jr , John ^a,c  

^a IEEE   (United States)

^b Conexant Systems Inc ^*  (United States)

^c University of Southern California   (United States)

^d Valence Semiconductor   (United States)

Author keywords

Clock generator; CMOS phase locked loop; Dc dc capacitive converter; Voltage regulator

Indexed keywords

CAPACITIVE CONVERTERS;

CMOS INTEGRATED CIRCUITS; JITTER; POWER CONVERTERS; SPURIOUS SIGNAL NOISE; VOLTAGE REGULATORS;

PHASE LOCKED LOOPS;

EID: 0035472555     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.953473     Document Type: Article

References (22)

1. A 360-MHz 3-V CMOS PLL with 1-V peak-peak power supply noise tolerance
2. A 0.35-μm CMOS 3-880-MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors
3. Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and +50-ps jitter
4. A 320-MHz 1.5-mW at 1.35-V CMOS PLL for microprocessor clock generator
5. A 600-MHz CMOS PLL microprocessor clock generator with a 1.2-GHz VCO
6. A 200-MHz CMOS phase-locked loop with dual phase detectors
7. t CMOS circuit for multiple on-chip power control
8. Cell-based fully integrated CMOS frequency synthesizers
9. Analyze PLL's with discrete time modeling
10. Charge-pump phase-locked loops
11. Analysis of timing jitter in CMOS ring oscillators
12. MOS operational amplifier design-A tutorial overview
13. An improved frequency compensation technique for CMOS operational amplifiers
14. Power supply rejection ratio in operational transconductance amplifiers
15. On-chip high-voltage generation in nMOS integrated circuits using an improved voltage multiplier technique
16. Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits
17. A dynamic analysis of the Dickson charge pump circuit
18. MOS charge pumps for low-voltage operation