A 4-GHz clock system for a high-performance system-on-a-chip design

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1693-1698

  Ingino, Joseph M ^a,b   Von Kaenel, Vincent R ^a,b  

^a IEEE   (United States)

^b BROADCOM CORPORATION   (United States)

Author keywords

Analog digital integrated circuits; Gain boosting; Phase locked loops; Supply noise

Indexed keywords

ACTIVE FILTERING; CHARGE PUMP TOPOLOGY; HIGH-SPEED DIVIDER DESIGN; PASSIVE FILTERING; PHASE FREQUENCY DETECTOR; POWER SUPPLY REJECTION RATIO; SYSTEM-ON-A-CHIP DESIGN;

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; JITTER; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

PHASE LOCKED LOOPS;

EID: 0035505585     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962289     Document Type: Article

References (10)

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