VLSI decoder architecture for high throughput, variable block-size and multi-rate LDPC codes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2104-2107

  Sun, Yang ^a   Karkooti, Marjan ^a   Cavallaro, Joseph R ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); ERROR CORRECTION; RANDOM PROCESSES; THROUGHPUT;

MULTI-RATE LDPC CODES; VARIABLE BLOCK-SIZES;

VLSI CIRCUITS;

EID: 34548851999     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378514     Document Type: Conference Paper

References (7)

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2. M.M. Mansour and N.R. Shanbhag, "A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip," IEEE Journal of Solid-State Circuits, vol. 41, pp. 684-698, March 2006.
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