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Volumn , Issue , 2007, Pages 2734-2737

Dynamic reconfigurability in embedded system design

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS;

EID: 34548830180     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378618     Document Type: Conference Paper
Times cited : (25)

References (28)
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    • Alberto Donato, Fabrizio Ferrandi, Marco D. Santambrogio, and Donatella Sciuto. Exploiting partial dynamic reconfiguration for soc design of complex application on fpga platforms. In IFIP VLSI-SOC 2005, pages 179-184, 2005.
    • (2005) IFIP VLSI-SOC 2005 , pp. 179-184
    • Donato, A.1    Ferrandi, F.2    Santambrogio, M.D.3    Sciuto, D.4
  • 2
    • 34548836405 scopus 로고    scopus 로고
    • F.Furtek. A field-programmable gate array for systolic computing. pages 183-199. Research on Integrated Systems: Proc. of the 1993 Symposium, G. Boriello and C. Ebeling, 1993.
    • F.Furtek. A field-programmable gate array for systolic computing. pages 183-199. Research on Integrated Systems: Proc. of the 1993 Symposium, G. Boriello and C. Ebeling, 1993.
  • 4
    • 34548840902 scopus 로고    scopus 로고
    • B.K. Fawcett. Applications of reconfigurable logic, pages 57-69. More FPGAs: Proc. of the 1993 International workshop on field-programmable logic and applications, W. Moore and W. Luk, 1993.
    • B.K. Fawcett. Applications of reconfigurable logic, pages 57-69. More FPGAs: Proc. of the 1993 International workshop on field-programmable logic and applications, W. Moore and W. Luk, 1993.
  • 5
    • 0037878328 scopus 로고    scopus 로고
    • P.C. French and R.W.Taylor. A self-reconfiguring processor. pages 50-59. Proc. of IEEE Workshop on FPGAs for Custom Computing Machine, D.A. Buell and K.L. Pocek, 1993.
    • P.C. French and R.W.Taylor. A self-reconfiguring processor. pages 50-59. Proc. of IEEE Workshop on FPGAs for Custom Computing Machine, D.A. Buell and K.L. Pocek, 1993.
  • 6
    • 34548862959 scopus 로고    scopus 로고
    • P. Lysaught, J. Stockwood, J. Law, and D. Girma. Artificial neural network implementation on a fine-grainde FPGA. R. Hartenstein and M.Z. Servit, 1994.
    • P. Lysaught, J. Stockwood, J. Law, and D. Girma. Artificial neural network implementation on a fine-grainde FPGA. R. Hartenstein and M.Z. Servit, 1994.
  • 8
    • 34548836664 scopus 로고    scopus 로고
    • A fast macro based compilation methodology for partially reconfigurable fpga designs
    • Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, and Ranga Vemuri. A fast macro based compilation methodology for partially reconfigurable fpga designs. In VLSI Design, pages 91-, 2003.
    • (2003) VLSI Design , pp. 91
    • Handa, M.1    Radhakrishnan, R.2    Mukherjee, M.3    Vemuri, R.4
  • 9
    • 0142039780 scopus 로고    scopus 로고
    • On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures
    • João M. P. Cardoso. On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures. IEEE Trans. Computers, 52(10):1362-1375, 2003.
    • (2003) IEEE Trans. Computers , vol.52 , Issue.10 , pp. 1362-1375
    • Cardoso, J.M.P.1
  • 12
    • 34548780538 scopus 로고    scopus 로고
    • In-Circuit Partial Reconfiguration of RocketIO Attributes
    • Technical Report XAPP662, Xilinx Inc, January
    • Vince Ech, Punit Kalra, Rick LeBlanc, and Jim McManus. In-Circuit Partial Reconfiguration of RocketIO Attributes. Technical Report XAPP662, Xilinx Inc., January 2003.
    • (2003)
    • Ech, V.1    Kalra, P.2    LeBlanc, R.3    McManus, J.4
  • 13
    • 48149107545 scopus 로고    scopus 로고
    • Early access partial reconfiguration guide
    • Xlinx
    • Xlinx. Early access partial reconfiguration guide. In UG208. Xlinx, 2006.
    • (2006) UG208
    • Xlinx1
  • 15
    • 34548823053 scopus 로고
    • Processor reconfiguration through instruction-set metamorphosis
    • H. F. Silverman. Processor reconfiguration through instruction-set metamorphosis. IEEE Computer, 1993.
    • (1993) IEEE Computer
    • Silverman, H.F.1
  • 20
    • 34548810019 scopus 로고    scopus 로고
    • Washington University, Department of Computer Science. Version 2.0, Technical Report
    • January
    • David E. Taylor, John W Lockwood, and Sarang Dharmapurikar. Generalized rad module interface specification of the field programmable port extender (fpx). Washington University, Department of Computer Science. Version 2.0, Technical Report, January 2000.
    • (2000)
    • Taylor, D.E.1    Lockwood, J.W.2    Dharmapurikar, S.3
  • 21
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    • Washington University, Department of Computer Science, Technical Report WUCS-01-13
    • July
    • Edson Horta and John W. Lockwood. Parbit: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (fpgas). Washington University, Department of Computer Science, Technical Report WUCS-01-13, July 2001.
    • (2001)
    • Horta, E.1    Lockwood, J.W.2
  • 27
    • 33750202678 scopus 로고    scopus 로고
    • Managing partial dynamic reconfiguration in virtex ii pro fpgas
    • Xilinx
    • Philippe Butel, Gerard Habay, and Alain Rachet. Managing partial dynamic reconfiguration in virtex ii pro fpgas. In Xcell Journal. Xilinx, 2004.
    • (2004) Xcell Journal
    • Butel, P.1    Habay, G.2    Rachet, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.