A fast macro based compilation methodology for partially reconfigurable FPGA designs

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 91-96

  Handa, M ^a   Radhakrishnan, R ^a   Mukherjee, M ^a   Vemuri, R ^a  

^a University of Cincinnati   (United States)

Author keywords

Algorithm design and analysis; Application software; Circuits; Field programmable gate arrays; Libraries; Logic devices; Program processors; Reconfigurable logic; Runtime; Silicon

Indexed keywords

APPLICATION PROGRAMS; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LIBRARIES; LOGIC DEVICES; LOGIC SYNTHESIS; MAPPING; NETWORKS (CIRCUITS); PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE; SILICON; SYSTEMS ANALYSIS;

ALGORITHM DESIGN AND ANALYSIS; APPLICATION SOFTWARES; BEHAVIORAL DESCRIPTIONS; PARTIALLY RECONFIGURABLE DEVICES; RECONFIGURABLE FPGA; RECONFIGURABLE LOGIC; RUNTIMES; TECHNOLOGY MAPPING;

MACROS;

EID: 34548836664     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183120     Document Type: Conference Paper

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