FPGA implementation of LDPC decoders based on joint row-column decoding algorithm

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1653-1656

  Zhiyong, He ^a   Roy, Sébastien ^a   Fortier, Paul ^a  

^a UNIVERSITÉ LAVAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LDPC DECODERS; LOW-DENSITY PARITY-CHECK (LDPC) CODES;

CODES (SYMBOLS);

EID: 34548829427     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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9. T. J. Richardson, "Error Floors of LDPC Codes", 41st Annual Allerton Conf. on Communications, Control and Computing, pp. 1426-1435, Monticello, Illinois, USA, Oct. 2003.