Impact of bottom interfacial layer on the threshold voltage and device reliability of fluorine incorporated PMOSFETs with high-k/metal gate

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2007, Pages 374-377

  Choi, Kisik ^a   Lee, Taeho ^b   Barnett, Joel ^a   Harris, Harlan R ^c   Kweon, Seungsoo ^b   Young, Chadwin ^a   Bersuker, Gennadi ^a   Choi, Rino ^a   Song, Seung Chul ^a   Lee, Byoung Hun ^d   Jammy, Rajaro ^d  

^a SEMATECH   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c AMD ^*

^d IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE DIELECTRICS; INTERFACES (MATERIALS); ION IMPLANTATION; RELIABILITY THEORY; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE;

DEVICE RELIABILITY; GATE STACKS; THERMALLY GROWN INTERFACIAL LAYERS;

MOSFET DEVICES;

EID: 34548805552     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2007.369918     Document Type: Conference Paper

References (8)

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2. H. Rusty Harris, Siddarth Krishnan, Huang-Chun Wen, Husam Alshareef, Aarthi Rao, Louis Solis, Prashant Majhi, Rino Choi, Byoung Hun Lee, Gennadi Bersuker and George A. Brown, "Reliability Characteristics of Metal/High-κ PMOS with Top Interface Engineered Band Offset Dielectric (BOD)", in Proc. 2006 IRPS, pp. 661-662 (2006)
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5. y/High-k Gate Stack for Enhanced Device Threshold Voltage Stability and Performance", in Proceedings of 2005 IEDM Tech. Dig. p. 713-716
6. Kang-ill Seo, Raghavasimhan Sreenivasan, Paul C. McIntyre, and Krishna C. Saraswat, "Improvement in High-k (HfO2/SiO2) Reliability by Incorporation of Fluorine", 2005 IEDM Tech. Dig. IEDM p. 429-432
7. K. Choi et al. to be published
8. Zhibo Zhang, Muhammad M. Hussain, Sang Ho Bae, S.C. Song, and Byoung Hun Lee, "Impact of Metal Wet Etch on Device Characteristics and Reliabilities for Dual Metal Gate/High-k CMOS", in Proc. 2006 IRPS, pp. 388-391