An efficient 3-bit-scan multiplier without overlapping bits, and its 64 x 64 bit implementation

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 441-446

  Yu, Hak Soo ^a   Abraham, J A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ECONOMIC AND SOCIAL EFFECTS; SEQUENTIAL CIRCUITS;

HIGH SPEED; LOW POWER; MULTIPLICATION OPERATIONS; PARTIAL PRODUCT; POWER DELAYS; TRADE OFF;

DESIGN;

EID: 84962247301     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994960     Document Type: Conference Paper

References (9)

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