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Volumn , Issue , 2007, Pages 159-164

Static and dynamic analysis of SEU effects in SRAM-based FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; NETWORKS (CIRCUITS); SENSITIVITY ANALYSIS; STATIC ANALYSIS; STATIC RANDOM ACCESS STORAGE;

EID: 34548728657     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2007.37     Document Type: Conference Paper
Times cited : (10)

References (12)
  • 5
    • 33646472893 scopus 로고    scopus 로고
    • A new reliabilityoriented place and route algorithm for SRAM-based FPGAs
    • June
    • L. Sterpone and M. Violante, "A new reliabilityoriented place and route algorithm for SRAM-based FPGAs", IEEE Transactions on Computers, Vol. 55, Issue 6, June, 2006, pp. 732 - 744.
    • (2006) IEEE Transactions on Computers , vol.55 , Issue.6 , pp. 732-744
    • Sterpone, L.1    Violante, M.2
  • 7
    • 34548730090 scopus 로고    scopus 로고
    • Estimation of Mean Time Between Failure Caused by Single Event Upset, Xilinx
    • Jan
    • P. Sundararajan and B. Blodget, "Estimation of Mean Time Between Failure Caused by Single Event Upset", Xilinx Application Notes, XAPP559, Jan. 2005.
    • (2005) Application Notes , vol.XAPP559
    • Sundararajan, P.1    Blodget, B.2
  • 8
    • 33144458550 scopus 로고    scopus 로고
    • An analytical approach for soft error rate estimation of SRAM-based FPGAs
    • G. Asadi and M. B. Tahoori, "An analytical approach for soft error rate estimation of SRAM-based FPGAs", presented at the MAPLD Conf., 2004.
    • (2004) presented at the MAPLD Conf
    • Asadi, G.1    Tahoori, M.B.2
  • 9
    • 33144481330 scopus 로고    scopus 로고
    • A new analytical approach to estimate the effects of SEUs in TMR architecture implemented through SRAM-based FPGAs
    • Dec
    • L. Sterpone and M. Violante, "A new analytical approach to estimate the effects of SEUs in TMR architecture implemented through SRAM-based FPGAs", IEEE Transactions on Nuclear Science, vol. 52, Issue 6, Dec. 2005, pp. 2217 - 2223.
    • (2005) IEEE Transactions on Nuclear Science , vol.52 , Issue.6 , pp. 2217-2223
    • Sterpone, L.1    Violante, M.2
  • 10
    • 11044235410 scopus 로고    scopus 로고
    • M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella, Simulation-based analysis of SEU effects in SRAMbased FPGAs, IEEE Transactions on Nuclear Science, 51, Issue 6, Part 2, Dec. 2004, pp. 3354 - 3359.
    • M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella, "Simulation-based analysis of SEU effects in SRAMbased FPGAs", IEEE Transactions on Nuclear Science, Vol. 51, Issue 6, Part 2, Dec. 2004, pp. 3354 - 3359.
  • 11
    • 34548142857 scopus 로고    scopus 로고
    • Triple Module Redundancy Design Techniques for Virtex FPGAs, Xilinx
    • C. Carmichael, "Triple Module Redundancy Design Techniques for Virtex FPGAs", Xilinx Application Notes, XAPP197,2001.
    • (2001) Application Notes , vol.XAPP197
    • Carmichael, C.1
  • 12
    • 34548741702 scopus 로고    scopus 로고
    • TMRTool User Guide, 2004, Xilinx User Guide, UG156
    • TMRTool User Guide, 2004, Xilinx User Guide, UG156


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.