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Volumn , Issue , 2007, Pages 1391-1396

Fast statistical circuit analysis with finite-point based transistor model

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; COMPUTATIONAL METHODS; CURRENT VOLTAGE CHARACTERISTICS; POLYNOMIALS; STATISTICAL METHODS; TRANSIENT ANALYSIS;

EID: 34548356683     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364492     Document Type: Conference Paper
Times cited : (13)

References (13)
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  • 2
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  • 3
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    • Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits
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    • Orshansky, M.1    Milor, K.2    Chen, P.3    Keutzer, K.4    Hu, C.5
  • 4
    • 0036049629 scopus 로고    scopus 로고
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    • Jun
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  • 5
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  • 6
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    • Cao, Y.1    Clark, L.2
  • 7
    • 0031078092 scopus 로고    scopus 로고
    • A physical and Scalable I-V Model in BSIM3v3 for Analog /Digital Circuit Simulation
    • Feb
    • Y. Cheng, et al., "A physical and Scalable I-V Model in BSIM3v3 for Analog /Digital Circuit Simulation," IEEE Trans. Electron Devices, vol. 44, no. 2, pp. 277-287, Feb. 1997.
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  • 8
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  • 9
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  • 10
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.