Estimating functional coverage in bounded model checking

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1176-1181

  Große, Daniel ^a   Kühne, Ulrich ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

MODEL CHECKING; PRODUCT DESIGN; PROGRAM PROCESSORS;

BOUNDED MODEL CHECKING (BMC); COVERAGE PROPERTY; FUNCTIONAL COVERAGE;

NETWORKS (CIRCUITS);

EID: 34548301397     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364454     Document Type: Conference Paper

References (18)

1. Accellera Property Specification Language Reference Manual, version 1.1. http://www.pslsugar.org, 2005.
2. M. Ali, A. Veneris, S. Safarpour, R. Drechsler, A. Smith, and M.S.Abadir. Debugging sequential circuits using Boolean satisfiability. In Int'l Conf. on CAD, pages 204-209, 2004.
3. N. Amla, X. Du, A. Kuehlmann, R. P. Kurshan, and K. L. McMillan. An analysis of SAT-based model checking techniques in an industrial environment. In Correct Hardware Design and Verification Methods (CHARME), pages 254-268, 2005.
4. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Tools and Algorithms for the Construction and Analysis of Systems, volume 1579 of LNCS, pages 193-207. Springer Verlag, 1999.
5. R. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans. on Comp., 35(8):677-691, 1986.
6. R. Bryant. Binary decision diagrams and beyond: Enabling techniques for formal verification. In Int'l Conf. on CAD, pages 236-243, 1995.
7. J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verification using symbolic model checking. In Design Automation Conf., pages 46-51, 1990.
8. H. Chockler, O. Kupferman, and M. Vardi. Coverage metrics for temporal logic model checking. In Tools and algorithms for the construction and analysis of systems, number 2031 in Lecture Notes in Computer Science, pages 528 - 542, 2001.
9. H. Chockler, O. Kupferman, and M. Y. Vardi. Coverage metrics for formal verification. In Correct Hardware Design and Verification Methods (CHARME), pages 111-125, 2003.
10. K. Claessen. A coverage analysis for safety property lists. Presentation at Workshop on Designing Correct Circuits (DCC), 2006.
11. E. M. Clarke, O. Grumberg, and A. Peled. Model Checking. MIT Press, 1999.
12. G. Fey and R. Drechsler. Improving simulation-based verification by means of formal methods. In ASP Design Automation Conf., pages 640-643, 2004.
13. G. Fey and R. Drechsler. SAT-based calculation of source code coverage for BMC. In GI/ITG/GMM-Workshop, 2006.
14. D. Große, U. Kühne, and R. Drechsler. Hw/sw coverification of embedded systems using bounded model checking. In Great Lakes Symp. VLSI, pages 43-48, 2006.
15. Y. V. Hoskote, T. Kam, P. Ho, and X. Zhao. Coverage estimation for symbolic model checking. In Design Automation Conf., pages 300-305, 1999.
16. N. Jayakumar, M. Purandare, and F. Somenzi. Dos and don'ts of ctl state coverage estimation. In Design Automation Conf., pages 292-295, 2003.
17. S. Katz and O. Grumberg. Have I written enough properties - a method of comparison between specification and implementation. In Correct Hardware Design and Verification Methods (CHARME), pages 280-297, 1999.
18. K. Winkelmann, H.-J. Trylus, D. Stoffel, and G. Fey. Costefficient block verification for a UMTS up-link chip-rate coprocessor. In Design, Automation and Test in Europe, volume 1, pages 162-167, 2004.