An analysis of SAT-based model checking techniques in an industrial environment

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3725 LNCS, Issue , 2005, Pages 254-268

  Amla, Nina ^a   Du, Xiaoqun ^a   Kuehlmann, Andreas ^a   Kurshan, Robert P ^a   McMillan, Kenneth L ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BDD-BASED MODEL CHECKING; BINARY DECISION DIAGRAMS (BDDS); HYBRID ALGORITHMS;

ALGORITHMS; BENCHMARKING; COMPUTER HARDWARE; COMPUTER SCIENCE; FINITE AUTOMATA; MATHEMATICAL MODELS;

FORMAL LANGUAGES;

EID: 33646392976     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11560548_20     Document Type: Conference Paper

References (29)

1. N. Amla, R. Kurshan, K. McMillan, and R. Medel. Experimental analysis of different techniques for bounded model checking. In TACAS, 2003.
2. N. Amla and K. McMillan. A hybrid of counterexample-based and proof-based abstraction. In FMCAD, 2004.
3. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In TACAS, 1999.
4. R. E. Bryant. Graph-based algorithms for boolean function manipulations. IEEE Transactions on Computers, 1986.
5. 20 states and beyond. In LICS, 1990.
6. P. Chauhan, E. Clarke, J. Kukula, S. Sapra, H. Veith, and D. Wang. Automated abstraction refinement for model checking large state spaces using sat based conflict analysis. In FMCAD, 2002.
7. E.M. Clarke and E. A. Emerson. Design and synthesis of synchronization skeletons using branching time temporal logic. In Workshop on Logics of Programs, 1981.
8. F. Copty, L. Fix, R. Fraer, E. Giunchiglia, G. Kamhi, A. Tacchella, and M. Vardi. Benefits of bounded model checking at an industrial setting. In CAV, 2001.
9. E. A. Emerson. Temporal and modal logic. In Handbook of Theoretical Computer Science, Volume B: Formal Models and Sematics, 1990.
10. M. Ganai, A. Gupta, and P. Ashar. Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. In ICCAD, 2004.
11. E. Goldberg and Y. Novikov. Berkmin: A fast and robust sat-solver. In DATE, 2002.
12. M. Iyer, G. Parthasarathy, and K.T. Cheng. SATORI- an efficient sequential SAT solver for circuits. In ICCAD, 2003.
13. H. Jin and F. Somenzi. CirCUs: Hybrid satisfiability solver. In SAT, 2004.
14. A. Kuehlmann. Dynamic transition relation simplification for bounded property checking. In ICCAD, 2004.
15. A. Kuehlmann, V. Paruthi, F. Krohm, and M. Ganai. Robust Boolean reasoning for equivalence checking and functional property verification. In TCAD, 2003.
16. O. Kupferman and M. Vardi. Model checking of safety properties. In Formal Methods in System Design, 2001.
17. R. Kurshan. Computer-aided Verification of Coordinating Processes: The Automata-Theoretic Approach. Princeton University Press, 1994.
18. B. Li, C. Wang, and F. Somenzi. A satisfiability-based approach to abstraction refinement in model checking. In Workshop on BMC, 2003.
19. J. Marques-Silva and K. Sakallah. GRASP: A search algorithm for prepositional satisfiability. IEEETC: IEEE Transactions on Computers, 48, 1999.
20. K. McMillan. Applying SAT methods in unbounded symbolic model checking. In CAV, 2003.
21. K. McMillan. Interpolation and SAT-based model checking. In CAV, 2003.
22. K. McMillan and N. Amla. Automatic abstraction without counterexamples. In TACAS, 2003.
23. M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an Efficient SAT Solver. In DAC, 2001.
24. G. Parthasarathy, M. Iyer, K.T. Cheng, and L.C. Wang. A comparison of BDDs, BMC, and sequential SAT for model checking. In High-Level Design Validation and Test Workshop, 2003.
25. M. Prasad, A. Biere, and A. Gupta. A survey of recent advances in sat-based formal verification. In STTT, 2005.
26. J.P. Queille and J. Sifakis. Specification and verification of concurrent systems in CESAR. In Proc. of the 5th International Symposium on Programming, 1982.
27. M. Sheeran, S. Singh, and G. Stalmarck. Checking safety properties using induction and a SAT-solver. In FMCAD, 2000.
28. C. Wang, B. Li, H. Jin, G. Hachtel, and F. Somenzi. Improving ariadne's bundle by following multiple threads in abstraction refinement. In ICCAD, 2003.
29. J. Whittemore, J. Kim, and K. Sakallah. Satire: A new incremental satisfiability engine. In DAC, 2001.