-
3
-
-
84944319371
-
Symbolic model checking without BDDs
-
Tools and Algorithms for the Construction and Analysis of Systems. Springer Verlag
-
A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Tools and Algorithms for the Construction and Analysis of Systems, volume 1579 of LNCS, pages 193-207. Springer Verlag, 1999.
-
(1999)
LNCS
, vol.1579
, pp. 193-207
-
-
Biere, A.1
Cimatti, A.2
Clarke, E.3
Zhu, Y.4
-
4
-
-
84947289900
-
SAT-based verification without state space traversal
-
Int'l Conf. on Formal Methods in CAD. Springer
-
P. Bjesse and K. Claessen. SAT-based verification without state space traversal. In Int'l Conf. on Formal Methods in CAD, volume 1954 of LNCS, pages 372-389. Springer, 2000.
-
(2000)
LNCS
, vol.1954
, pp. 372-389
-
-
Bjesse, P.1
Claessen, K.2
-
5
-
-
26444589672
-
SyCE: An integrated environment for system design in SystemC
-
R. Drechsler, G. Fey, C. Genz, and D. Große. SyCE: An integrated environment for system design in SystemC. In IEEE International Workshop on Rapid System Prototyping, pages 258-260, 2005.
-
(2005)
IEEE International Workshop on Rapid System Prototyping
, pp. 258-260
-
-
Drechsler, R.1
Fey, G.2
Genz, C.3
Große, D.4
-
7
-
-
34547743138
-
Modellierung eines mikroprozessors in SystemC
-
D. Große, U. Kühne, C. Genz, F. Schmiedle, B. Becker, R. Drechsler, and P. Molitor. Modellierung eines Mikroprozessors in SystemC. In ITG/GI/GMM-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", 2005.
-
(2005)
ITG/GI/GMM-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
-
-
Große, D.1
Kühne, U.2
Genz, C.3
Schmiedle, F.4
Becker, B.5
Drechsler, R.6
Molitor, P.7
-
9
-
-
0034852165
-
Chaff: Engineering an efficient SAT solver
-
M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Design Automation Conf., pages 530-535, 2001.
-
(2001)
Design Automation Conf.
, pp. 530-535
-
-
Moskewicz, M.1
Madigan, C.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
10
-
-
70350787997
-
Checking safety properties using induction and a SAT-solver
-
Int'l Conf. on Formal Methods in CAD. Springer
-
M. Sheeran, S. Singh, and G. Stålmarck. Checking safety properties using induction and a SAT-solver. In Int'l Conf. on Formal Methods in CAD, volume 1954 of LNCS, pages 108-125. Springer, 2000.
-
(2000)
LNCS
, vol.1954
, pp. 108-125
-
-
Sheeran, M.1
Singh, S.2
Stålmarck, G.3
-
11
-
-
33750911444
-
-
Synopsys Inc., CoWare Inc., and Frontier Design Inc.
-
Synopsys Inc., CoWare Inc., and Frontier Design Inc., http://www.systemc.org. Functional Specification for SystemC 2.0.
-
Functional Specification for SystemC 2.0
-
-
-
12
-
-
3042511934
-
Cost-efficient block verification for a UMTS up-link chip-rate coprocessor
-
K. Winkelmann, H.-J. Trylus, D. Stoffel, and G. Fey. Cost-efficient block verification for a UMTS up-link chip-rate coprocessor. In Design, Automation and Test in Europe, volume 1, pages 162-167, 2004.
-
(2004)
Design, Automation and Test in Europe
, vol.1
, pp. 162-167
-
-
Winkelmann, K.1
Trylus, H.-J.2
Stoffel, D.3
Fey, G.4
|