A 5.2-GHz CMOS receiver with 62-dB image rejection

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 5, 2001, Pages 810-815

  Razavi, Behzad ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Heterodyne architecture; Image reject architecture; Low noise amplifiers; Mixers; Offset cancellation; RF CMOS design; RF receivers

Indexed keywords

GAUSSIAN MINIMUM SHIFT KEYING; HETERODYNE ARCHITECTURE; IMAGE REJECTION; LOW NOISE AMPLIFIERS; OFFSET CANCELLATION; RADIO FREQUENCY RECEIVERS;

DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; LOCAL AREA NETWORKS; MIXER CIRCUITS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; OSCILLATORS (ELECTRONIC); QUADRATURE AMPLITUDE MODULATION; RADIO FREQUENCY AMPLIFIERS; RADIO RECEIVERS; SPURIOUS SIGNAL NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 0035335240     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.918919     Document Type: Article

References (9)

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