Quaternary look-up tables using voltage-mode CMOS logic design

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2007, Pages

  Cunha, Ricardo ^a   Boudinov, Henri ^a   Carro, Luigi ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LOGIC DESIGN;

BINARY LOGIC; MULTIPLE-VALUED LOGIC; QUATERNARY LOGIC FUNCTIONS;

TABLE LOOKUP;

EID: 34548225396     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISMVL.2007.47     Document Type: Conference Paper

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