Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Berg, Y ^a   Aunet, S ^b   Mirmotahari, O ^a   Hovin M ^a  

^a UNIVERSITY OF OSLO   (Norway)

^b NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PROCESSING; DIGITAL CIRCUITS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); NUMERICAL METHODS; SHORT CIRCUIT CURRENTS; SIGNAL PROCESSING;

POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS;

EID: 0038420740     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. K.C. Smith "The prospects of multivalued logic systems", In IEEE Transactions on Computers, vol C-30, no. 9, pp. 619-634, September 1981.
2. T. Shibata and T. Ohmi. " A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", In IEEE Transactions on Electron Devices, vol 39, 1992.
3. K. Kotani, T. Shibata, M. Imai and T. Ohmi. "Clocked-Neuron-MOS Logic Circuits Employing Auto-ThresholdAdjustment", In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.
4. Y. Berg, S. Aunet and M. Hoøvin. "On the Potential of Recharge Multiple-Valued CMOS Logic", Submitted to the IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, may 2003.
5. R. Lashevsky, K. Takaara and M. Souma "Neuron MOSFET as a Way to Design a Threshold Gates with the Threshold and Input Weights Alterable in Real Time", IEEE TT13.11-1.4, 1998, pp. 263-266.
6. Y. Berg, Ø. Næss, S. Aunet, J. Lomsdalen and M. Hoøvin. "A novel Floating-Gate Binary signal to Multiple-Valued signal Converter for Multiple-Valued CMOS Logic", In IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dubrovnik, September 2002.