A novel voltage-mode CMOS quaternary logic design

IEEE Transactions on Electron Devices

Volumn 53, Issue 6, 2006, Pages 1480-1483

  da Silva, Ricardo Cunha G ^a   Boudinov, Henri ^a   Carro, Luigi ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Inverter; Multiple valued logic (MVL) circuits; NMAX; NMIN; Voltage mode quaternary CMOS design

Indexed keywords

COMPUTER SIMULATION; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; THRESHOLD VOLTAGE; TRANSISTORS;

CMOS DESIGN; MULTIPLE-VALUED LOGIC (MVL) CIRCUITS; QUATERNARY LOGIC GATES; THRESHOLD VOLTAGE TRANSISTORS; VOLTAGE-MODE QUATERNARY;

CMOS INTEGRATED CIRCUITS;

EID: 33744811190     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.874751     Document Type: Article

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