Multi-path routing for mesh/torus-based NoCs

Proceedings - International Conference on Information Technology-New Generations, ITNG 2007

Volumn , Issue , 2007, Pages 734-739

  Jiao, Yaoting ^a   Yang, Yulu ^a   He, Ming ^a   Yang, Mei ^b   Jiang, Yingtao ^b  

^a NANKAI UNIVERSITY   (China)

^b UNIVERSITY OF NEVADA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA ACQUISITION; DATA COMMUNICATION EQUIPMENT; ELECTRIC DELAY LINES; NETWORK ROUTING; SEMICONDUCTOR DEVICES;

CROSSTALK NOISE; TRANSPORT MODEL; WIDER SPACING;

MULTI AGENT SYSTEMS;

EID: 34548130189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITNG.2007.129     Document Type: Conference Paper

References (11)

1. L. Benini and G. DeMicheli, "Networks on chips: a new SoC paradigm," Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
2. Crosstalk calculation and analysis, available at: http://www.eetchina. com/ARTICLES/2004MAY/1/2004MAY10_BD_NTFORUM01.HTM.
3. W.J. Dally, "A VLSI architecture for concurrent data structures," PH.D. Dissertation, Dep. Comput. Sci., California Instit. Technol., Tech. Rep. 5209:TR:86, 1986.
4. W.J. Dally and C.L. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Trans. Computers, vol. C-36, no. 5, pp. 547-553, May 1987.
5. W.J. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks," Proc. Design Automation Conf (DAC), 2001, pp. 684-689.
6. N. Eisley and L-S. Peh, "High-level power analysis for on-chip networks," Proc. CASES, 2004, pp. 22-25.
7. A. Jantsch and H. Tenhunen, Networks on Chip, Kluwar Academic Publishers, 2003.
8. N. Kavaldjiev and G. M. Smit, "An energy-efficient network-on-chip for a heterogeneous tiled reconfigurable systems-on-chip," Proc. Euromicro Symp. Digital System Design (DSD), 2004, pp. 492-498.
9. K. Lee, S-J. Lee and H-J. Yoo, "SILENT: serialized low energy transmission coding for on-chip interconnection networks," IEEE Int'l Conf. Computer Aided Design (ICCAD), 2004, pp. 448-451.
10. P. Magarshack and P. G. Paulin, "System-on-chip beyond the nanometer wall," Proc. Design Automation Conf. (DAC), 2003, pp. 419-424.
11. D. Rossi, C. Metra, A. K. Nieuwland, and A. Katoch, "Exploiting ECC redundancy to minimize crosstalk impact," IEEE Design & Test of Computers, vol. 22, no. 1, pp. 59-70 , Jan 2005.