Exact grading of multiple path delay faults

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 84-88

  Padmanaban, Saravanan ^a   Tragoudas, Spyros ^a  

^a Southern Illinois University at Carbondale   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATPG TOOLS; FAULT GRADING; MEMORY PROBLEMS; MULTIPLE-PATH; PATH DELAY FAULT; POLYNOMIAL NUMBER; TEST SETS; ZERO-SUPPRESSED BINARY DECISION DIAGRAMS;

EXHIBITIONS; GRADING; TESTING;

ELECTRIC FAULT CURRENTS;

EID: 34548126273     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998253     Document Type: Conference Paper

References (10)

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2. Gharaybeh M. A., Bushnell M. L. and Agrawal V. D., An exact non-enumerative fault simulator for path-delay faults, Proc. of International Test Conference, 1996, pp. 276-285.
3. Ke W. and Menon P.R., Synthesis of Delay-Verifiable Combinational Circuits, IEEE Trans. on Computers, vol. 44, pp.213-222, Feb. 1995.
4. Michael M., and Tragoudas S., ATPG for Path Delay Faults without Path Enumeration, Proc. International Symposium on Quality of Electronic Design, March 2001.
5. Michael M., and Tragoudas S., ATPG for Path Delay Faults at Functional Level, to appear in ACM Trans. on Design Automation of Electronic Systems, Vol. 7, No. 1, Jan. 2002.
6. Minato S-I., Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems, Proc. of Design Automation Conference, 1993, pp. 272-277.
7. Minato S-I., Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs, Proc. of Design Automation Conference, 1994, pp. 420-424.
8. Padmanaban S., Michael M. and Tragoudas S., Exact Path Delay Grading with Fundamental BDD Operations, Proc. of International Test Conference, 2001, pp.642-651.
9. Pant P., Yuan .C.H., Gupta. S.K. and Chatterjee A., Path Delay Fault Diagnosis in Combinational Cicuits with Implicit Fault Enumeration, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 10, Oct. 2001,pp. 1226-1235.
10. Tragoudas S. and Denny N., Testing of Path Delay Faults using Test Points, Proc. of IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1999, pp.86-94.