Exact path delay grading with fundamental BDD operations

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 642-651

  Padmanaban, S ^a   Michael, M ^a   Tragoudas, S ^a  

^a SOUTHERN ILLINOIS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMBINATORIAL MATHEMATICS; COMPUTER SIMULATION; DECISION THEORY; POLYNOMIALS;

BINARY DECISION DIAGRAMS (BDD);

INTEGRATED CIRCUIT TESTING;

EID: 0035687354     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966684     Document Type: Article

References (18)

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13. Model for delay faults based upon paths
14. Accurate path delay fault coverage is feasible
15. Testing for path delay faults using test points